Verilog: Mux 2 to 1 (Multiplexer)

Understanding the low levels always helps me to know and learn better and touch the reality of computers, particularly when I am coding.

Mux 2 to 1 (Multiplexer) is one of the easiest digital circuits which is made by different gates such as AND and OR gates.

The point of the 2-to-1 multiplexer is that can help you to select your chosen input. For example, you have i0 and i1 as Input One and Input Two, and you need to select between inputs. You can set a Select to decide which inputs must transfer to output (F).

In the truth table you can see if you set your select equals to 0, then the first Input which is i0 (a) will choose and vice versa.

To implement this module you need to know what gates you need.

It consists of two AND, one OR, and one NOT gates.
The boolean logic equation for a 2-to-1 multiplexer is
(A. ˉS)+(B. S)
where A is the first input and B is the second input.

embed module mux2to1(sel, i1, i0, f);
    input i0, i1, sel;
    output f;
    wire nsel, w1, w2;

    not(nsel, sel);

    and(w1, i0, nsel);
    and(w2, i1, sel);
    or(f, w1, w2);
endmodule

To evaluate the code you can check it manually or write a testbench for it.

module test_mux2to1;
  reg s, a1, a0;
  wire q;
  mux2to1 mux(.sel(s), .i1(a1), .i0(a0), .f(q));
  initial begin
    $monitor("sel = %b: i0 = %b, i1 = %b --> f = %b", s, a0, a1, q);
    s = 1'b0; a1=1'b0; a0=1'b0;
    #10
    s = 1'b0; a1=1'b1; a0=1'b1;
    #10
    s = 1'b0; a1=1'b1; a0=1'b0;
    #10
    s = 1'b0; a1=1'b1; a0=1'b1;
    #10
    s = 1'b1; a1=1'b0; a0=1'b0;
    #10
    s = 1'b1; a1=1'b0; a0=1'b1;
    #10
    s = 1'b1; a1=1'b1; a0=1'b0;
    #10
    s = 1'b1; a1=1'b1; a0=1'b1;
  end
endmodule

The code is available on my GitHub. Here is the link.