Skippable introduction

During this lockdown (like almost everyone) I have a lot of free time, so I decidedto give a look at my to do list.In the looong term goals part where you can find impossible goals like "savethe world" or "learn haskell" there was "learn vhdl", too.

Now or never

That's what I thought. So here I am, reading the awesome free range vhdl bookand getting started with the first examples.I am debugging my nonsense signals produced by my nonsense code with VivadoWebPACK, which has some limitations, but it's free and it's a decent tool if you are learning.

Why writing tests

Anyway, getting the output right and going to the next exercise reminded me ofold dark ages when I was hacking my main and adding print everywhere to know ifmy code was working.Yes, your code might work now, when the sun is high and you haven't touched asingle comma of your codebase. But what if new requirements comes in or you have tofix a bug? You will unavoidably have to change your code. At that point how willyou be sure that you didn't break anything?

Yes, tests is the right answer. 💯And once you get used to them I can ensure you will never go back!In particular, I get used to repeatable tests and big green check marks thatensure you that your program does not work only on your computer and that youhaven't forget to git add some files.

So I thought: "why don't I try to setup Continuous integration for a VHDL project?" 😀

CI for VHDL

Easy, right? Unfortunately there was no GitHub actions that matched the word"vhdl" on the github actions marketplace. And there's a very good reason forthat. Hardware description languages like VHDL or Verilog are not like commonprogramming languages where nowadays everything is open source.Most of the people, uses whatever the FPGA makerprovides them, which includes proprietary libraries and so on and of course thisstuff is not intended to be used with docker and things like that.

Anyway, for my simple examples I didn't need vendor proprietary libraries,therefore I was free to explore open source solutions to run and tests my code 😀

I choose to use ghdl (an open-source simulator for the VHDL language)and vunit (an open source unit testing framework for VHDL/SystemVerilog).

It turns out that there is a really handy docker image hosted on the dockerhub, which provides both vunit and ghdl.

It was super easy to create a GitHub action based on this image, so meet VunitAction, a GitHub action that let you do CI with your VHDL projects!You can find how I used this action in my vhdl examples.

So yes, finally there is at least one match for the word "vhdl" in the Githubaction Marketplace 😅