danishhilman

Posted on Sep 19, 2023

CPU Simulator

#beginners #python #codecademy

This is my portfolio project for CS104: Computer Architecture. The project objectives are as follows:

Use Git version control
Use the command line and file navigation
Develop locally on your computer
Design and implement a working Python program that simulates the -- inner workings of a CPU

This program simulates the functionalities of a CPU, Cache, and a Main Memory. 11 instructions from the MIPS32 Instruction Set are implemented in the program.

CPU

32 General Purpose Registers:

1 Internal Register:

curr_instruction

The curr_instruction register stores the current instruction ready for processing.

2 Special Purpose Registers:

PC

The PC or Program Counter stores the memory address of the instruction that should be processed next. Initially the PC is set to 0.

cache_status

Either True or False; if True Cache On, if False Cache Off.

The CPU's instruction cycle:

Fetch
Decode
Execute
*Memory Access
*Registry Write-Back

*This stage only occurs if necessary

Fetch

During this stage the CPU fetches the instruction from the address stored in the PC then increments PC to point to the next instruction

Decode

In this stage the Control Unit deciphers what the instruction stored in the curr_instruction means. For example, the instruction could have been sent to do an arithmetic operation or to send information to another piece of hardware. As the instruction is decoded, they are turned into a series of control signals that are used to execute the instruction.

Execution

The next stage in the cycle involves performing the instruction. During the decoding stage, the instruction is decoded into control signals and sent to the correct part of the ALU (Arithmetic Logic Unit) to be processed and completed.

Memory Access

This stage is used to read/write to the main memory or cache to fulfil a request by an instruction

Registry Write-Back

During the registry write-back stage, new data is stored to one of the registers in the CPU. The registry write-back stage is also necessary if existing data is changed or updated.

Main Memory

The main memory is equipped with 16 memory locations used for storing any data types.

Cache

The cache is equipped with 4 blocks responsible for holding copies of main memory data.

Replacement Policy

FIFO

First In First Out; The data is replaced in the order it was placed in the cache.

Associativity

2-way set-associative

A set-associative cache maps each memory location to a specified number of locations in cache. In this case the cache has 4 blocks and is 2-way set-associative therefore it has 2 blocks per set. Each main memory location maps to a set based on the location address, the formula for finding the set based on the location address: set_number = address modulo number_of_sets

Write Policy

Write-Back

The write-back policy writes data to the cache but only writes the data to the main memory when the data is about to be replaced in the cache.

Instruction Set Manual:

RD - DESTINATION REGISTER
RS, RT - SOURCE OPERAND REGISTERS
RA - RETURN ADDRESS REGISTER (R31)
PC - PROGRAM COUNTER

INSTRUCTIONS, OPERANDS:

    ADD, Rd, Rs, Rt
        MEANING
            Rd <- Rs + Rt
    ADDI, Rt, Rs, immd
        MEANING
            Rt <- Rs + immd

    SUB, Rd, Rs, Rt
        MEANING
            Rd <- Rs - Rt

    SLT, Rd, Rs, Rt
        MEANING
            If (Rs < Rt) then Rd <- 1 else Rd <- 0

    BNE, Rs, Rt, offset
        MEANING
            If (Rs not equal Rt) then PC <- (PC + 4) + offset * 4

    SW, Rt, offset, Rs
        MEANING
            MEM[Rs + offset] <- Rt
    LW, Rt, offset, Rs
        MEANING
            Rt <- MEM[Rs + offset]

    CACHE, code
        MEANING
            Code = 0(Cache off), Code = 1(Cache on), Code = 2(Flush cache)

    J, target
        MEANING
            PC <- target * 4
    JAL, target
        MEANING
            RA <- PC + 4; PC <- target *4

    HALT, ;
        MEANING
            Terminate Execution

All Instructions are inputted to the "instruction_input.txt" file. Instructions are separated by "\n" (newline) and parameters are separated by ",".

Example inputted instructions:

CACHE,1
ADDI,1,1,1
ADDI,2,2,2
ADD,3,2,1
SW,3,3,3
SW,3,4,3
SW,3,5,3
SW,3,6,3
LW,9,3,3
LW,10,4,3
LW,11,5,3
LW,12,6,3
SW,1,7,3
SW,3,3,3
CACHE,0
SW,2,8,3
CACHE,1
SW,2,9,3
CACHE,2
HALT,;

For now, this program can accomplish additions, subtractions, check equality, alter the flow of program execution, implement function calls and subroutines, store/load data to or from memory and cache functionalities for faster retrieval of data by the processor.

Links

Github repo: CPU-Simulator

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