We are using the Analog Devices HDL reference design for the zc706 and ADRV9371. We got a clock error when we connected up our IP (DVB-S2 Encoder).
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /dvbs2_encoder_wrapper_0/s_axis(100000000) and /axi_ad9371_tx_dma/m_axis(200000000)
ERROR: [BD 41-237] Bus Interface property CLK_DOMAIN does not match between /dvbs2_encoder_wrapper_0/s_axis(system_sys_ps7_0_FCLK_CLK0) and /axi_ad9371_tx_dma/m_axis(system_sys_ps7_0_FCLK_CLK1)
This error doesn't happen when we do this:
ad_connect axi_ad9371_tx_dma/m_axis_last dvbs2_encoder_wrapper_0/s_axis_tlast
ad_connect axi_ad9371_tx_dma/m_axis_valid dvbs2_encoder_wrapper_0/s_axis_tvalid
ad_connect axi_ad9371_tx_dma/m_axis_ready dvbs2_encoder_wrapper_0/s_axis_tready
ad_connect axi_ad9371_tx_dma/m_axis_data dvbs2_encoder_wrapper_0/s_axis_tdata
But it does when we do this:
ad_connect axi_ad9371_tx_dma/m_axis dvbs2_encoder_wrapper_0/s_axis
In looking at how ad_connect is defined in .../scripts/adi_board.tcl:
proc ad_connect {name_a name_b} {
set type_a [ad_connect_int_class $name_a]
set type_b [ad_connect_int_class $name_b]
set obj_a [ad_connect_type $name_a]
set obj_b [ad_connect_type $name_b]
if {!([string first intf $type_a]+1) != !([string first intf $type_b]+1)} {
error "ERROR: ad_connect: Cannot connect non-interface to interface: $name_a ($type_a) <-/-> $name_b ($type_b)"
}
The first thing it does is compare interface types. That's how I learned AXI Smartconnect was the wrong choice (in one of two ways) for trying to upsize the bus to the DACFIFO.
There's then a large switch case statement to return the names and types in question.
After the switch case statement is:
# Continue working on nets that connect to constant. obj_b is the net/pin
set width [ad_connect_int_width $obj_b]
set cell [ad_connect_int_get_const $name_a $width]
connect_bd_net [get_bd_pin $cell/dout] $obj_b
puts "connect_bd_net [get_bd_pin $cell/dout] $obj_b"
}
connect_bd_net is a Xilinx tcl command. ad_connect is an ADI command (defined as described above in .../scripts/adi_board.tcl)
The link to the connect_bd_net documentation is https://docs.xilinx.com/r/en-US/ug835-vivado-tcl-commands/connect_bd_net
Maybe, when running ad_connect, it runs connect_bd_net, gets all the pins with get_bd_pin, and hooks up a lot more than the few signals we believe we need. We think it's connecting the AXI clock (ACLK) in a different place than we intend.
We will just keep learning how to connect things and use TCL until everything works!
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