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Discussion on: What was your win this week?

sachindas246 profile image

I have started working on a new language similar to verilog ( for defining logic circuits) but more simpler. I have posted it on the dev, but after working on it for sometime I have came across lot of difficulties. And understood the mistakes in the way I have defined it. Fortunately I have found the solutions for them . And I would mention them in the coming post.
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