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Donald Sebastian Leung
Donald Sebastian Leung

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Getting started with OSDev on RISC-V

I recently re-gained interest in RISC-V after my initial encounter with it in the second half of 2020 through my co-op internship at M-Labs. In case you haven't heard of RISC-V, it's an openly documented RISC ISA that any individual or commercial hardware vendor can freely implement. Apart from its openness, it boasts a highly modular structure which organizes the specification into a minimal base ISA plus a myriad of optional extensions, enabling highly flexible RISC-V compliant processor designs suited for a wide variety of use cases.

In order to familiarize myself with RISC-V from a programmer's perspective, I've experimented with the following over the past two months (August-September 2022):

As a logical next step to exploring the RISC-V landscape, I've decided to investigate how to take full control of the hardware by writing a RISC-V operating system from scratch.

Current progress (2022-09-10)

Over the past few days, I've managed to implement a rudimentary RISC-V operating system kernel in C that does little more than print stuff to the serial console. Nevertheless, I did my best to structure the project to facilitate development in the mid- to long-term. The project template which I'll build upon going forward is released on GitHub as v0.0.1 of maRVelOS code-named "Meaty Skeleton", so if you're also interested in RISC-V and open hardware as a programmer, feel free to follow along!

I also noticed that the OSDev Wiki is lacking articles and resources on RISC-V at the time of writing, so I took the opportunity to create an account there and contribute my first article, RISC-V Meaty Skeleton with QEMU virt board, in the hopes that it would be useful to the wider OSDev community. As you might have guessed, OSDev stands for "operating systems development" and the OSDev community is where hobbyists in operating systems development gather together to exchange knowledge and ideas.

Resources and acknowledgements

I would like to thank the authors of RISC-V from scratch and The Adventures of OS for their high-quality articles that go into great detail on how RISC-V works. Without their well-written articles, I wouldn't have known how to get started with kernel development on RISC-V. My initial project setup - the minimal C runtime crt0.s in assembly and the linker script riscv64-virt.lds - is based on the former, while my UART driver code is adapted from the latter and I intend to closely follow the latter going forward.

For the cross-compiler toolchain, I referred to the relevant page on the OSDev wiki, and I adapted the instructions from both OSDev and (Beyond) Linux From Scratch for building my cross-GDB targeting 64-bit RISC-V.

My adventure has just begun

maRVelOS can only print stuff to the console at the time of writing. It still can't do a lot of basic stuff expected of a typical operating system:

  • Memory management
  • Process management
  • Handling interrupts
  • Reading and writing files
  • ...

It's probably going to take me a long while before I manage to get anywhere near a borderline usable system, but hopefully I'll stick with it and learn more about the hardware from a programmer's perspective along the way. After all, the main takeaway of OSDev is the learning experience - for an out-of-the-box production grade general-purpose OS kernel, Linux is the answer ;-)

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